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rev. prb | page 1 of 17 16 bit 4lsb vout nano dac tm , buffered, 3v/5v, sot 23 preliminary technical data ad5061 features single 16-bit dac, 4 lsb inl. 1.8 volt digital interface capability power-on-reset to zero volts/mid scale three power-down functions low power serial interface with schmitt- triggered inputs 8-lead sot23 low power operation fast settling. low glitch on powerup. applications process control data acquisition systems portable battery powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators general description the ad5061, a member of the nano dac tm family, is a single 16-bit buffered voltage out dac, available in a 8 ld sot23. the ad5061 can be operated at 3v/5v. the part utilizes a versatile three-wire serial interface that operates at clock rates up to 30 mhz and is compatible with standard spi?, qspi?, microwire? and dsp interface standards. the reference for the ad5061 is supplied from an external ref pin. a reference buffer is also provided on chip. the parts incorporate a power-on-reset circuit that ensures that the dac output powers up to zero volts/ mid scale and remains there until a valid write takes place to the device. the parts also contain a power-down feature that reduces the current consumption of the device to 50na at 5 v and provides software selectable output loads while in power-down mode. the part is put into power-down mode over the serial interface. total unadjusted error for the part is <1mv. these parts also provide a very low glitch on power-up. ad5061 part number description ad5062 2.7 v to 5.5 v, 16 bit nano dac tm d/a, 1lsbs inl., unbuffered, sot 23. ad5063 2.7 v to 5.5 v, 16 bit nano dac tm d/a, 1 lsbs inl., unbuffered, 10 usoic, uncommi tted bi-polar resistors. ad5040/60 2.7 v to 5.5 v, 14/16 bit nano dac tm d/a, 1 lsbs inl, buffered, sot23. product highlights 1. available in 8-lead sot23. 2. 16 bit accurate, 4 lsb inl. 3. low glitch on power-up. 4. high speed serial interface with clock speeds up to 30 mhz. 5. three power down modes available to the user. rev. prb information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved.
ad5061 preliminary technical data rev. prb | page 2 of 17 ad5061specifications 1 ad5061, v dd = 5.5v, vref =4.096v, rl=5k, 200pf . t min to t max ; unless otherwise noted. parameter b version 1 min typ max unit test conditions/comments static performance ad5061 resolution 16 bits relative accuracy 4 lsb tue 0.5 mv differential nonlinearity 1 lsb guaranteed monotonic by design. offset 0.65 uv zer code error 100 uv gain error 200 uv offset drift 6 v/c gain temperature coefficient 2.5 ppm of fsr/c output characteristics output voltage range 0 v ref -150mv v output voltage settling time 10 s 1/4 to 3/4 to +/-1lsb slew rate 1 v/s capacitive load stability 470 pf rl= 1000 pf rl = 5k output noise spectral density 50 nv/ hz dac code=tbd , 1khz 50 nv/ hz dac code=tbd , 10khz digital-to-analog glitch impulse 5 nv-s 1 lsb change around major carry. digital feedthrough 0.5 nv-s dc output impedance 1 ? reference input/ouput vref input range 2 v dd-100mv v input current 1 ua dc input impedance 1 m ? logic inputs input current 1 a v inl , input low voltage 0.8 v v dd = +5 v v inh , input high voltage 1.8 v v dd = +5 v v inl , input low voltage 0.6 v v dd = +3 v v inh , input high voltage 1.4 v v dd = +3 v pin capacitance 3 pf power requirements v dd 2.7 3.6 v ad5060 (3 volt option) i dd (normal mode) dac active and excluding load current v dd = +2.7 v to +3.6 v 900 a v ih = v dd and v il = gnd i dd (all power-down modes) v dd 5.0 5.5 v ad5060 (5 volt option) i dd (normal mode) dac active and excluding load current v dd = +5.0 v to +5.5 v 1.3 ma v ih = v dd and v il = gnd i dd (all power-down modes)
preliminary technical data ad5040/ad5060 rev. prb | page 3 of 17 parameter b version 1 min typ max unit test conditions/comments v dd 2.7 5.5 v ad5040 i dd (normal mode) dac active and excluding load current v dd = +2.7 v to +5.5 v i dd (all power-down modes) 50 na v ih = v dd and v il = gnd pssr 0.5 lsb vdd +/- 10% notes 1 temperature ranges are as follows: b vers ion: C40c to +125c, typical at 25c. 2 guaranteed by design and characterization, not production tested. 3 linearity calculated using a reduced code range 480-64716. specifications subject to change without notice.
ad5061 preliminary technical data rev. prb | page 4 of 17 timing characteristics (v dd = 2.7-5.5 v; all specifications t min to t max unless otherwise noted) parameter limit 1 unit test conditions/comments t 1 3 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 12 ns min sclk low time t 4 13 ns min sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 33 ns min minimum sync high time t 9 13 ns min sync rising edge to next sclk fall ignore . notes 1 all input signals are specified with tr = tf = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 2 see figure 1. 3 maximum sclk frequency is 30 mhz. specifications subject to change without notice. figure 1. timing diagramad506. ad5040 has same timing specs with 14 bit word.
preliminary technical data ad5040/ad5060 rev. prb | page 5 of 17 absolute maximum ratings table 1. absolute maximum ratings (t a = 25c unless otherwise noted) parameter rating v dd to gnd C0.3 v to + 7.0 v digital input voltage to gnd C0.3 v to v dd + 0.3 v v out to gnd 1 C0.3 v to v dd + 0.3 v operating temperature range industrial (b version) C40c to +125c storage temperature range C65c to +150c maximum junction temperature 150c sot23 package power dissipation (tj max-ta)/ ja ja thermal impedance 229.6c/w jc thermal impedance 91.99c/w lead temperature, soldering vapour phase (60 sec) 300c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly; functional operation of the device at these or any other conditions above those listed in the operational sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <2 kv, and it is esd sensitive. proper precaution s should be taken for handling and assembly. model temperature range inl description package options ad5061brj-1 -40 o c to 125 o c 4 lsb 5v, buffered dac in sot-23, reset to zero rt8 ad5061brj-2 -40 o c to 125 o c 4 lsb 5v, buffered dac in sot-23, reset to mid rt8 ad5061brj-3 -40 o c to 125 o c 4 lsb 3v, buffered dac in sot-23, reset to zero rt8
ad5061 preliminary technical data rev. prb | page 6 of 17 pin configuration and function description figure 2. ad5063 8 ld sot23 table 2. pin function descriptions mnemonic function v dd power supply input. these parts can be operated from +2.5 v to +5.5 v and v dd should be decoupled to gnd. ref reference voltage input. dacgnd ground input to the dac. v out analog output voltage from dac. sync level triggered control input (active lo w). this is the frame synchronizatio n signal for the input data. when sync goes low, it enables the input shift register and data is transferred in on the falling edges of the following cloc ks. the dac is update d following the 16th clock cycle unless sync is taken high before this edge in which case the rising edge of sync acts as an interrupt and the write sequence is ignored by the dac. sclk serial clock input. data is cloc ked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates up to 30 mhz. d in serial data input. this device has a 24 bi t shift register. data is clocked into the register on the falling edge of the serial clock input. agnd ground reference point for analog circuitry on the part.
preliminary technical data ad5040/ad5060 rev. prb | page 7 of 17 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviatio n, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 2. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 3. zero-code error zero-code error is a measure of the output error when zero code (0000hex) is loaded to the dac register. ideally the output should be 0 v. the zero-c ode error is always positive in the ad5061 because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in mv. a plot of zero-code error vs. temperature can be seen in figure 6. full-scale error full-scale error is a measure of the output error when full-scale code (ffff hex) is loaded to the dac register. ideally the output should be v dd C 1 lsb. full-scale error is expressed in percent of full-scale range. a plot of full-scale error vs. temperature can be seen in figure 6. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal expressed as a percent of the full-scale range. total unadjusted error total unadjusted error (tue) is a measure of the output error taking all the various errors in to account. a typical tue vs. code plot can be seen in figure 4. zero-code error drift this is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv secs and is measured when the digital input code is changed by 1 lsb at the major carry transi tion (7fff hex to 8000 hex). see figure 19. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nv secs and measured with a full-scale code change on the data bus, i.e ., from all 0s to all 1s and vice versa.
ad5061 preliminary technical data rev. prb | page 8 of 17 inl linearity plot -1 -0.6 -0.2 0.2 0.6 1 dac code lsb figure 3. typical inl plot figure 4. total unadjusted error polt. figure 5. zero scale error and full scale error vs. temperature dnl linearity plot -1 -0.6 -0.2 0.2 0.6 1 dac code lsb figure 6. typical dnl plot. figure 7. inl & dnlvs supply figure 8. idd histogram @ vdd=3/5 volts.
preliminary technical data ad5040/ad5060 rev. prb | page 9 of 17 figure 9. source and sink current capability figure 10. supply current vs. temperature figure 11. full scale settling time figure 12. supply current vs code. figure 13. supply current vs supplyovoltage figure 14. half scale settling time
ad5061 preliminary technical data rev. prb | page 10 of 17 figure 15. power on reset to 0 volts. figure 16. digital to analog glitch impulse figure 17. output spectral density 100k bandwidth figure 18. exiting power-down figure 19. harmonic distortion on igitally generated waveform. figure 20. 0.1 hz to 10 hz noise plot
preliminary technical data ad5040/ad5060 rev. prb | page 11 of 17 figure 21. powerup transient figure 22. glitch energy figure 23. offset error distribution figure 24. gain error distribution
ad5061 preliminary technical data rev. prb | page 12 of 17 general description the ad5061 is a single 16-bit, serial input, voltage output dacs. the ad5061 operates from either a 3v or 5v supply. data is written to the ad50461in a 24-bit word format. the ad5061 incorporates a power-on reset circuit, which ensures that the dac output powers up to 0 v or mid-scale. the device also has a software power-down mode pin, which reduces the typical current consumption to 50na at 3v. dac architecture the dac architecture of the ad5061 consists of two matched dac sections. a simplifed circuit diagram is shown in figure x the four msbs of the 16-bit data word are decoded to drive 15 switches, e1 to e15. each of these switches connects one of 15 matched resistors to either agnd or vref. the remaining 12 bits of thedata word drive switches s0 to s11 of a 12-bit voltage moder-2r ladder network. figure x. dac ladder structure reference buffer the ad5061 operates with an external reference. the reference input (refin) has an input range of up to vdd. this input voltage is then used to provide a buffered reference for the dac core serial interface the ad5061 (24 bit word write) has a three-wire serial interface (sync, sclk and din), which is compatible with spi, qspi and microwire interface standards as well as most dsps. see figure 1 for a timing diagram of a typical write sequence. the write sequence begins by bringing the sync line low. data from the din line is clocked into the 24-bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 30 mhz, making the se parts compatible with high speed dsps. on the 24 th falling clock edge, the last data bit is clocked in and the programmed function is executed (i.e., a change in dac register contents and/or a change in the mode of operation). at this stage, the sync line may be kept low or be brought high. in either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of sync can initiate the next write sequence. since the sync buffer draws more current when v in = 1.8 v than it does when v in = 0.8 v, sync should be idled low between write sequences for even lower power operation of the part. as is mentioned above, however, it must be brought high again just before the next write sequence. input shift register the input shift register is 24 bits wide (see figure 22/23). d23- d16 are set to zero for normal op eration. d17, d16 are control bits that control which mode of operation the part is in (normal mode or any one of three power- down modes). there is a more complete description of the various modes in the power- down modes section. the next sixteen bits are the data bits. these are transferred to the dac register on the 24th falling edge of sclk. figure 22. ad5060 input register contents
preliminary technical data ad5040/ad5060 rev. prb | page 13 of 17 figure 22. ad5040 input register contents sync interrupt in normal write sequence, the sync line is kept low for at least 24 falling edges of sclk and the dac is updated on the 24th falling edge. however, if sync is brought high before the 24th falling edge this acts as an interrupt to the write sequence. the shift register is reset and the write sequence is seen as invalid. neither an update of the dac register contents or a change in the operating mode occurssee figure 23. power-on-reset the ad5061 contains a power-on-res et circuit that controls the output voltage during power-up . the dac register is filled with zeros and the output voltage is zero volts/mid-scale. it remains there until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. software reset. the ad5061 can be put into software reset by setting all in the dac register to one. this includes writing ones to bits d23- d16, which in not the normal mode of operation. note: the sync interrupt command cannot be performed if a software reset command is started. power-down modes the ad5061 contains three separate modes of operation. these modes are software-programmable by setting two bits (pd1 and pd0) in the control register. table i shows how the state of the bits corresponds to the mode of operation of the device. table i. modes of operation for the ad5061 pd1 pd0 operating mode 0 0 normal operation power-down mode 0 1 tri-state 1 0 100 k ? to gnd 1 1 1 k ? to gnd * when both bits are set to 0, the part works normally with its normal power consumption. ho wever, for the three power- down modes, the supply current falls to 200 na at 5 v (50 na at 3 v). not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the part is known while the part is in power-down mode. there are three different options. the output is c o n nected internally to gnd through a 1k ? resistor, a 100 k ? resistor or it is left open-circuited (three-state ). the output stage is illustrated in figure 24. figure 24. output stage during power-down the bias generator, the output amplifier, the dac and other associated linear circuitry are all shut down when the power-down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s for v dd = 3 v. see figure 18 for a plot.
ad5061 preliminary technical data rev. prb | page 14 of 17 microprocessor interfacing ad5061 to adsp-2101/adsp-2103 interface figure 25 shows a serial inte rface between the ad5061 and the adsp-2101/adsp-2103. the adsp-2101/adsp-2103 should be set up to operate in the sp ort transmit alternate framing mode. the adsp-2101/adsp-2103 sport is programmed through the sport control regist er and should be configured as follows: internal clock operation, active low framing, 16- bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. figure 25. ad5061 to adsp-2101/adsp-2103 interface db23 db0 sclk sync din db23 db0 valid write sequence, output updates invalid write sequence: sync high before 24 th falling edge on the 24 th falling edge figure 23. sync interrupt facility for ad5060. ad5061 to 68hc11/68l11 interface figure 26 shows a serial inte rface between the ad5060 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5060, while the mosi output drives the serial data line of the dac. the sync signal is derived from a port li ne (pc7). the setup conditions for correct operation of this interface are as follows: the 68hc11/68l11 should be configured so that its cpol bit is a 0 and its cpha bit is a 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 is configured as above, data appearing on the mosi output is valid on the fall ing edge of sck. serial data from the 68hc11/68l11 is transmit ted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. in orde r to load data to the ad5061, pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac and pc7 is taken high at the end of this procedure. figure 26. ad5061 to 68hc11/68l11 interface ad5061 to blackfin ad sp-bf53x interface figure 2x shows a serial interface between the ad5641 and the blackfin adsp-53x microprocessor. the adsp-bf53x processor family incorporates two dual-cha nnel synchronous serial ports, sport1 and sport0 for serial and multiprocessor communications. using sport0 to connect to the ad5062/63, the setup for the interface is as follow s. dt0pri drives the sdin pin of the ad5062/63, while tsclk0 drives the sclk of the part. the sync is driven from tfs0. figure 2x. ad5061 to blackfin adsp-bf53x interface ad5061 to 80c51/80l51 interface figure 27 shows a serial inte rface between the ad5061 and the 80c51/80l51 microcontroller. the se tup for the interface is as follows: txd of the 80c51/80l51 drives sclk of the ad5061, while rxd drives the serial data line of the part. the sync signal is again derived from a bit programmable pin on the port. in this case port line p3.3 is used. when data is to be transmitted to the ad5061, p3.3 is taken low. the 80c51/80l51 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low
preliminary technical data ad5040/ad5060 rev. prb | page 15 of 17 after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 outputs the serial data in a format which has the lsb first. the ad5061 requires it s data with the msb as the first bit received. the 80c51/8 0l51 transmit routine should take this into account. figure 27. ad5061 to 80c51/80l51 interface ad5061 to microwire interface figure 28 shows an interfac e between the ad5061 and any microwire compatible device. serial data is shifted out on the falling edge of the serial cloc k and is clocked into the ad5061 on the rising edge of the sk. figure 28. ad5061 to microwire interface applications choosing a reference for the ad5061. to achieve the optimum pe rformance from the ad5060, thought should be given to the choice of a precision voltage reference. the ad5061 have just one reference input, refin. the voltage on the reference input is used to supply the positive input to the dac . therefore any error in the reference will be reflected in the dac. there are 4 possible sources of error when choosing a voltage reference for high accuracy appl ications; initial accuracy, ppm drift, long term drift and output voltage noise. initial accuracy on the output voltage of the dac will lead to a full scale error in the dac. to minimize these errors , a reference with high initial accuracy is preferred. also, choos ing a reference with an output trim adjustment, such as the adr425 allow a system designer to trim system errors out by setting a reference voltage to a voltage other than the nominal. the trim adjustment can also be used at temperature to trim out any error. figure 29. adr425 as refere nce to ad5040. adr420 can be used for ad5060. long term drift is a measure of how much the reference drifts over time. a reference with a tight long term drift specification ensures that the overall soluti on remains relatively stable during its entire lifetime. the temperature co-efficient of a references output voltage affect inl,dnl tue. a reference with a tight temperature co- efficient specification should be chosen to reduce temperatue dependence of the dac output voltage on ambient conditions. in high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. choosing a reference with as low an output noise voltage as practical for the system noise resolution required is important. precision voltage references such as the adr435 produce low output noise in the 0.1-10hz region. examples of some recommended precision references for use as supply to the ad5060 are shown in the figure below.. part list of precision references for use with ad5061. part no. initial accuracy (mv max) temp drift (ppm o c max) 0.1-10hz noise (uv p-p typ) adr420 +/-6 3 1.75 adr425 +/-6 3 3.4 adr02 +/-5 3 15 adr392 +/-6 25 5 bipolar operation using the ad5061 the ad5061 has been designed fo r single-supply operation but a bipolar output range is also possible using the circuit in figure 30. the circuit below will give an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. the output voltage for any input code can be calculated as follows:
ad5061 preliminary technical data rev. prb | page 16 of 17 where d represents the input code in decimal (0C65535). with v dd = 5 v, r 1 = r 2 = 10 kw: this is an output voltage range of 5 v with 0000hex corresponding to a C5 v output and 3fff hex corresponding to a +5 v output. figure 30. bipolar operation with the ad5061 using ad5061 with an opto-isolated interface chip. in process-control applications in industrial environments it is often necessary to use an opto-isolated interface to protect and isolate the controlling circuitry from any hazardous common- mode voltages that may occur in the area where the dac is functioning. because the ad5061 uses a three-wire serial logic interface, the adum130xifamily s an ideal way to provide digital isolation for the dac interface. the adum130x isolators provide three independent isolation channels in a variety of channel configurations and data rates. they operate across the full range from 2.7v to 5.5v, providing compatibility with lower voltage systems as well as enabling a voltage translation functionalit y across the isolation barrier. figure 31. the power supply to the part also needs to be isolated. this is done by using a transformer. on the dac side of the transformer, a +5 v regulator provides the +5 v supply required for the ad5061. 0.1 . f +5v regulator v out gnd din sclk power 10 . f v dd sclk data dac sdi admu103x sdi v1a v1b v1c voa vob voc figure 31. ad5061 with an opto-isolated interface power supply bypassing and grounding when accuracy is important in a circuit it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit boar d containing the ad5061 should have separate analog and digita l sections, each having its own area of the board. if the ad506 1 is in a system where other devices require an agnd to dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5061. the power supply to the ad5061 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be physically as close as possible to the device with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effectiv e series resistance (esr) and effective series inductance (esi), e.g., common ceramic types of capacitors. this 0.1 f capa citor provides a low impedance path to ground for high freq uencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. cloc ks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces ar e placed on the solder side. however, this is not always possible with a two-layer board.
preliminary technical data ad5040/ad5060 rev. b | page 17 of 17 outline dimensions dimensions shown in inches and mms 8 ld sot23 ? 2004analog devices, inc. all rights reserved. trademarks and registered trademarks are the proper ty of their respective companies. pr04762-0-9/04(prb) .

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